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NXP Semiconductors /LPC11Axx /CT32B0 /PWMC

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Interpret as PWMC

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (EM0)PWMEN0 0 (EM1)PWMEN1 0 (EM2)PWMEN2 0 (EM3)PWMEN3 0RESERVED

PWMEN0=EM0, PWMEN1=EM1, PWMEN3=EM3, PWMEN2=EM2

Description

PWM Control Register. The PWMCON enables PWM mode for the external match pins CT32Bn_MAT[3:0].

Fields

PWMEN0

PWM mode enable for channel0.

0 (EM0): CT32Bi_MAT0 is controlled by EM0.

1 (PWM_MODE_IS_ENABLED_): PWM mode is enabled for CT32Bi_MAT0.
PWMEN1

PWM mode enable for channel1.

0 (EM1): CT32Bi_MAT01 is controlled by EM1.

1 (PWM_MODE_IS_ENABLED_): PWM mode is enabled for CT32Bi_MAT1.
PWMEN2

PWM mode enable for channel2.

0 (EM2): CT32Bi_MAT2 is controlled by EM2.

1 (PWM_MODE_IS_ENABLED_): PWM mode is enabled for CT32Bi_MAT2.
PWMEN3

PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle.

0 (EM3): CT32Bi_MAT3 is controlled by EM3.

1 (PWM_MODE_IS_ENABLED_): PWM mode is enabled for CT132Bi_MAT3.
RESERVED

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data